A monolithic integrated circuit is a combination of interconnected subcircuits containing circuit elements that are inseparably associated on or within a continuous substrate. Typically, the circuit elements are conventional components, transistors, diodes, capacitors, and resistors fabricated in situ within or on a single crystal of semiconductor material with the capability of performing a complete electronic circuit function.
In practice, an integrated circuit is designed in a top-down method by first designing a logic level drawing and a transistor level drawing. These drawings then are used to design the more detailed integrated circuit layout, which shows the IC layers (i.e.,, metal, polysilicon, and active, and the ways the layers interrelate to form transistor gates, wires, contact points, etc.). The integrated circuit layout, often referred to as "geometry," is used to generate the integrated circuit tooling, which is a series of masks, each representing a layer for the integrated circuit. The tooling is then used by manufacturers to fabricate an integrated circuit.
Typically, monolithic integrated circuits are fabricated by a process of photolithography, doping, and material deposition. Photolithography is any technique whereby light or other electromagnetic rays are shone through a mask to create a pattern on a silicon wafer coated with a photosensitive film. Doping includes those techniques for treating the exposed areas in the pattern to take on n- or p-type characteristics to form components of transistors and diodes. "Material deposition" refers to the growth or deposit of photoresist, insulating oxide, metal, polysilicon, and other materials that form the topology of the circuit.
In one method for fabricating an integrated circuit, a layer of photoresistive material is deposited on a semiconductor wafer. A mask for the integrated circuit is then placed over the layer of photoresistive material and light is shone through the mask to activate parts of the photoresistive material. This leaves a predetermined pattern of conductors on the wafer and exposed areas of the wafer between the conductors. Transistors and diodes are formed by doping portions of the exposed areas of the wafer with a chemical doping agent. A second mask can then be used to generate another pattern of conductors and exposed areas which are, once again, doped.
Additional doping layers may also be used. After each doping step, the photoresistive material is chemically removed from the wafer. When the final doping layer has been completed, a pattern of exposed areas of the wafer is once again formed by exposing a layer of photoresist on the wafer through a mask. A layer of metal or other suitable conductor is then deposited onto portions of the exposed areas of the semiconductor wafer to form the desired interconnections between components on the wafer. Though there are many fabrication technologies, fabrication techniques, and integrated circuit materials, fabricating the design for the integrated circuit through one or more masks is used consistently.
Depending on the fabrication technologies and techniques, and the materials used, different configuration constraints apply. These constraints are commonly referred to as "geometric design rules" or "design rules." Design rules include, for example, specifications for minimum spacing between transistors and minimum separation between conductors to prevent shorting, specifications for minimum metal width, and specifications for maximum metal heights and slopes of walls which form metal junctions.
With the continued improvement of fabrication technologies and techniques and the development of new materials used in defining electronic circuits, design rules are changing to allow for smaller and smaller spacings between materials on an integrated circuit and to allow smaller and smaller substrate areas. Thus design rules may change during the development process of any particular circuits. Because increases in the die size of a mask by fifteen percent typically result in a doubling of the cost of an integrated circuit, minimal substrate areas are desired.
Once the layout of a subcircuit has been determined, a designer would like to be assured that the wire connections of the layout are correct. This can be accomplished by comparing a transistor model of the layout with the connectivity of the original subcircuit. After the connectivity of the layout has been verified, its performance can be studied by means of a behavior simulation model. Such a simulation model includes a timing model for each cell of the subcircuit, including both digital and analog circuitry.
In U.S. Pat. No. 4,635,208, issued Jan. 6, 1987, Coleby et al. describe a method for computer-aided design of systems which binds three aspects of a circuit together. The three aspects bound together in the disclosure of the Coleby et al. patent are the circuit's logical model, its electrical circuit layout, and its mechanical design. By binding these three aspects together, Coleby et al. disclose a graphical, computer-performed method in which changes in any one of the three aspects of the system are reflected in changes in all of the three aspects and in their documentation.
In their patent, Coleby et al. do not disclose a system for establishing the constraints that are determined by a specified process technology. Neither do they disclose creating a layout geometry for the subcircuit according to the constraints. This follows naturally since they have not disclosed a system for establishing the constraints.
However, Coleby et al. do disclose steps of generating one or more simulation models for the layout geometry and generating a connectivity test model for the layout geometry that are known in the prior art. Specifically, FIG. 2 of the Coleby et al. patent, as described beginning on line 27 of its column 3, depicts a typical prior art technique for designing an electrical circuit with computer graphic techniques. This typical prior art technique includes designing an electrical schematic and extracting a net list (designating the connectivity of the circuit) therefrom. Simulation is performed on the mechanical layout. However, this typical prior art technique does not disclose, and cannot disclose, the steps of designing an electrical schematic and extracting a net list therefrom unless the layout geometry is established, and the layout geometry cannot be created until the constraints that are determined by a specific process technology are established.
In "Standard Cell VLSI Design: A Tutorial," IEEE Circuits and Devices Magazine, January 1985, pp. 17-33, Kessler et al. describe a very large scale integrated (VLSI) circuit design using standard cells. The layout of a standard cell, as stated in column 2 of page 17 of the Kessler et al. article, implies the interconnection of predefined and pre-laid out function blocks using a routing program.
Using a standard cell approach obviates both the need to establish the constraints that are determined by a specified process technology and the need to create a layout geometry for a circuit according to the constraints. The reason is that these steps are performed when a standard cell library is developed and recorded for later use. Accordingly, a person skilled in the art clearly knew in 1985 to specify a connectivity file from the layout geometry and then to use the connectivity file to generate one or more simulation models for the layout geometry. This is shown in FIG. 2 of the Kessler et al. article and in the corresponding text beginning with the heading "Schematic Capture of Design Intent" in column 1 of page 22. Accordingly, calculating the connectivity of each of the features of a particular layout and developing a simulation model of the timing performance of each of the models was known to a person skilled in the art as of January 1985.
While it has been known in the past to verify the connectivity of a given layout from the desired subcircuit, the required transistor model has heretofore been produced manually after the layout has been plotted. Allowing the transistor model to be developed from the module specification before the layout is created avoids the time-consuming task of producing the layout and rendering the transistor model from that layout. In addition, it is no longer necessary to develop the timing model from a plot of the layout after the connectivity of the layout has been verified, since the layout is dependent upon the process technology.
After a layout satisfying all of the constraint requirements has been developed, certain features on the layout can typically be enlarged and/or moved within the layout without changing the overall dimensions of the subcircuit. Heretofore, these desirable steps were necessarily handled on a one-by-one basis after the layout had been developed. In circuits and subcircuits of the complexity fostered by very large scale integration, this process can be tedious and time-consuming. It is therefore desirable to perform such steps rapidly after a layout has been initially designed.